2 nm process
In semiconductor manufacturing, the 2 nm process is the next MOSFET (metal–oxide–semiconductor field-effect transistor) die shrink after the 3 nm process node. As of 2021, TSMC is expected to begin 2 nm production sometime after 2024;[1] Intel also forecasts production by 2024,[2] followed by South Korean chipmaker Samsung for 2025.[3]
Semiconductor device fabrication |
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MOSFET scaling (process nodes) |
The term "2 nanometer" or alternatively "20 angstrom" (a term used by Intel) has no relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors. It is a commercial or marketing term used by the semiconductor chip fabrication industry to refer to a new, improved generation of silicon semiconductor chips in terms of increased transistor density (i.e. a higher degree of miniaturization), increased speed and reduced power consumption.[4][5]
Background
In late 2018, TSMC chairman Mark Liu predicted chip scaling would continue to 3 nm and 2 nm nodes;[6] however, as of 2019, other semiconductor specialists were undecided as to whether nodes beyond 3 nm could become viable.[7]
TSMC began research on 2 nm in 2019.[8] TSMC expected to transition from FinFET to GAAFET transistor types when moving from 3 nm to 2 nm.[9]
Intel's 2019 roadmap scheduled potentially equivalent 3 nm and 2 nm nodes for 2025 and 2027 respectively.[10] In December 2019, Intel announced plans for 1.4 nm production in 2029.[10]
In August 2020, TSMC began building a R&D lab for 2 nm technology in Hsinchu, expected to become partially operational by 2021.[11] In September 2020 (SEMICON Taiwan 2020) it was reported that TSMC Chairman Mark Liu had stated the company would build a plant for the 2 nm node at Hsinchu in Taiwan, and that it could also install production at Taichung dependent on demand.[12] According to the Taiwan Economic Daily (2020) expectations were for high yield risk production in late 2023.[13][14] In July 2021, TSMC received governmental approval to build its 2 nm plant; according to Nikkei the company expects to install production equipment for 2 nm by 2023.[15]
At the end of 2020, seventeen European Union countries signed a joint declaration to develop their entire semiconductor industry, including developing process nodes as small as 2 nm, as well as designing and manufacturing custom processors, assigning up to 145 billion euro in funds.[16][17]
In May 2021, IBM announced it had produced 2 nm class transistor using three silicon layer nanosheets with a gate length of 12 nm.[18][19][20]
In July 2021, Intel unveiled its process node roadmap from 2021 onwards. The company confirmed their 2 nm process node called Intel 20A,[notes 1] with the "A" referring to angstrom, a unit equivalent to 0.1 nanometer.[21] At the same time they introduced a new process node naming scheme that aligned their product names to similar designations from their main competitors.[22] However Intel 20A (same as 2nm) is actually a 5nm process going by existing industry naming standards.[23] Intel's 20A node is projected to be their first to move from FinFET to Gate-All-Around transistors (GAAFET); Intel's version is named 'RibbonFET'.[22] Their 2021 roadmap scheduled the Intel 20A node for introduction in 2024.[22]
Beyond 2 nm
Intel has planned 18A (equivalent to 1.8 nm) production for 2024, products after 2024.[21][2]
Notes
- Under Intel's previous naming scheme this node was known as 'Intel 5 nm'.[21]
References
- "TSMC Roadmap Update: 3nm in Q1 2023, 3nm Enhanced in 2024, 2nm in 2025". AnandTech. 18 October 2021.
- "Intel Technology Roadmaps and Milestones". Intel. 17 February 2022.
- "Samsung Foundry: 2nm Silicon in 2025". AnandTech. 6 October 2021.
- "TSMC's 7nm, 5nm, and 3nm "are just numbers… it doesn't matter what the number is"". Retrieved 20 April 2020.
- Samuel K. Moore (21 July 2020). "A Better Way to Measure Progress in Semiconductors: It's time to throw out the old Moore's Law metric". IEEE Spectrum. IEEE. Retrieved 20 April 2021.
- Patterson, Alan (12 September 2018), "TSMC: Chip Scaling Could Accelerate", www.eetimes.com, archived from the original on 24 September 2018, retrieved 23 September 2020
- Merritt, Rick (4 March 2019), "SPIE Conference Predicts Bumpy Chip Roadmap", www.eetasia.com, archived from the original on 27 June 2019, retrieved 23 September 2020
- Zafar, Ramish (12 June 2019), TSMC To Commence 2nm Research In Hsinchu, Taiwan Claims Report, archived from the original on 7 November 2020, retrieved 23 September 2020
- "Highlights of the day: TSMC reportedly adopts GAA transistors for 2nm chips", www.digitimes.com, 21 September 2020, archived from the original on 23 October 2020, retrieved 23 September 2020
- Cutress, Ian, "Intel's Manufacturing Roadmap from 2019 to 2029: Back Porting, 7nm, 5nm, 3nm, 2nm, and 1.4 nm", www.anandtech.com, archived from the original on 12 January 2021, retrieved 23 September 2020
- Wang, Lisa (26 August 2020), "TSMC developing 2nm tech at new R&D center", taipeitimes.com, archived from the original on 24 January 2021, retrieved 23 September 2020
- Chien-Chung, Chang; Huang, Frances (23 September 2020), "TSMC to build 2nm wafer plant in Hsinchu", focustaiwan.tw, archived from the original on 25 October 2020, retrieved 23 September 2020
- Udin, Efe (23 September 2020), "TSMC 2NM PROCESS MAKES A SIGNIFICANT BREAKTHROUGH", www.gizchina.com
- 台积电2nm工艺重大突破!2023年风险试产良率或达90% (in Chinese), 22 September 2020
- "Taiwan gives TSMC green light for most advanced chip plant". Nikkei Asia. Retrieved 24 August 2021.
- Dahad, Nitin (9 December 2020), "EU Signs €145bn Declaration to Develop Next Gen Processors and 2nm Technology", www.eetimes.eu, archived from the original on 10 January 2021, retrieved 9 January 2021
- Joint declaration on processors and semiconductor technologies, EU, 7 December 2020, archived from the original on 11 January 2021, retrieved 9 January 2021
- Nellis, Stephen (6 May 2021), "IBM unveils 2-nanometer chip technology for faster computing", Reuters, archived from the original on 7 May 2021, retrieved 6 May 2021
- Johnson, Dexter (6 May 2021), "IBM Introduces the World's First 2-nm Node Chip", IEEE Spectrum, archived from the original on 7 May 2021, retrieved 7 May 2021
- 12nm gate length is the dimension defined by the IRDS 2020 to be associated with the "1.5nm" process node:
- Cutress, Dr Ian (26 July 2021). "Intel's Process Roadmap to 2025: with 4nm, 3nm, 20A and 18A?!". www.anandtech.com. Retrieved 27 July 2021.
- Santo, Brian (27 July 2021), "Intel Charts Manufacturing Course to 2025", www.eetimes.com
- "What Is Intel 20A? The Process-Node Classification Explained". Digital Trends. 17 August 2021. Retrieved 2 May 2022.
Further reading
- Merritt, Rick (26 March 2018), "2nm: End of the Road ?", www.eetasia.com
Preceded by 3 nm (FinFET/GAAFET) |
MOSFET semiconductor device fabrication process | Succeeded by unknown |